The present invention generally relates to semiconductor integrated circuits, and more particularly to a voltage generator circuit used in a semiconductor integrated circuit for producing a voltage that is different from a supply voltage supplied to the semiconductor integrated circuit.
In large scale integrated circuits, various d.c. voltages are used for substrate biasing, word line driving, and the like. For example, a negative voltage of -3.5 volts is used conventionally for the substrate biasing. For the word line driving, a positive voltage of +7.5 volts is used. These d.c. voltages are produced based upon a supply voltage that is supplied to the integrated circuit. In the conventional integrated circuit, a voltage of +5 volts has been used for the supply voltage.
In the recent semiconductor integrated circuits having an increased integration density, there is a tendency that the magnitude of the supply voltage is reduced in correspondence to the increased integration density. In correspondence to such a reduction in the supply voltage, the substrate bias voltage is reduced from -3.5 volts to about -1 volt for example. It will be noted that such a decrease in magnitude of the supply voltage and the bias voltage reduces the reverse bias voltage applied to the p-n junctions formed in the integrated circuit.
In the large scale integrated circuits, there is a tendency that the substrate bias voltage, provided by a voltage generator circuit, fluctuates in response to the state of operation of the semiconductor devices on the chip. For example, when a large number of transistors are activated simultaneously, a large substrate current flows and the magnitude of the substrate bias voltage is reduced correspondingly. This effect becomes particularly conspicuous when a bias generator having a large internal resistance is employed, as such bias generators generally have a limited output power for driving the load. When a circuit having a small internal resistance is used, on the other hand, there is a tendency that the power consumption is increased excessively. It should be noted that such a circuit consumes a large electric power even in the stand-by state.
In order to avoid the foregoing problem, there is proposed a voltage generator circuit for use in semiconductor integrated circuits wherein the operation of the voltage generator circuit is controlled adaptively in response to the substrate bias voltage. In these conventional voltage generator circuits, the supply voltage is converted once to an a.c. voltage, and a desired d.c. voltage is obtained by converting the a.c. voltage again to a d.c. voltage. The regulation of the output d.c. voltage is thereby achieved by turning on and turning off an a.c. voltage generator that is used in the voltage generator for producing the a.c. voltage.
FIG. 1 shows the circuit diagram of the conventional voltage generator disclosed in the Japanese Laid-open Patent Application 59-193056. Referring to FIG. 1, the circuit includes a ring oscillator 102 that is supplied with a d.c. supply voltage Vcc and produces an a.c. voltage in response thereto. The a.c. voltage thus produced is transferred to a charge pump 103 via an output buffer circuit 104, wherein the charge pump 103 produces the desired d.c. output voltage V.sub.BB. The ring oscillator 102 is formed by connecting a number of CMOS inverters in series, while the charge pump 103 forms a voltage doubling rectifier including diodes D1 and D2 and a capacitor C.
In operation, the charge pump 103 produces an output voltage in proportion with the amplitude and the frequency of the output a.c. voltage of the ring oscillator 102 as the voltage V.sub.BB, wherein the turning-on and turning-off of the ring oscillator 102 is achieved by a control circuit 101 that compares the output voltage V.sub.BB with a reference voltage V.sub.REF. Thus, when the voltage V.sub.BB is decreased below the reference voltage V.sub.REF in response to the increase of the load, the control circuit 101 activates the ring oscillator 102 and the decrease in the voltage V.sub.BB is compensated. When the voltage V.sub.BB is increased above the reference voltage V.sub.REF, on the other hand, the control circuit 101 disables the ring oscillator 102.
As will be easily understood from the foregoing operation, the conventional circuit of FIG. 1 has a problem of large voltage swing between the state in which the ring oscillator 102 is activated and the state in which the ring oscillator 102 is deactivated. Generally, such a voltage swing compensates the voltage fluctuation of V.sub.BB excessively and the problem of the stability of the bias voltage V.sub.BB is even deteriorated, particularly in the recent large scale integrated circuits that use the small supply voltage Vcc and the correspondingly small bias voltage V.sub.BB. For example, the output voltage V.sub.BB of the conventional voltage generator circuit generally shows the voltage fluctuation of about 2.5 volts or more in response to the activation and deactivation of various semiconductor devices on the chip of the integrated circuit. Thus, in order to guarantee the minimum bias voltage of -1.0 volt, one has to set the nominal bias voltage V.sub.BB of the voltage generator circuit to a level of -3.5 volts or more. However, such a large bias voltage increases the reverse biasing applied to the p-n junction formed in the devices on the integrated circuit. In the recent large scale integrated circuits characterized by the high integration density, use of such a large bias voltage increases the risk of causing the breakdown of the devices on the integrated circuit.
FIG. 2 shows another conventional voltage generator circuit, wherein the circuit includes a first voltage generator unit B1 for producing the output voltage V.sub.BB with a large output power, and a second voltage generator unit B2 for producing the output voltage V.sub.BB with a small output power. The first voltage generator unit B1 consumes a large electric power while the second voltage generator unit B2 consumes little electric power. In the stationary state, the first voltage generator unit B1 is disabled for saving the electric power, and the control of the substrate biasing is achieved by the second voltage generator unit B2. Only when there is an increased load and associated drop of the bias voltage, which the second voltage generator B2 cannot compensate, the first voltage generator unit B1 is activated. For this purpose, a controller similar to the controller 101 is provided for detecting the variation of the bias voltage V.sub.BB Thus, the controller 101 activates the voltage generator unit B1 only when the bias voltage V.sub.BB has decreased below a reference voltage V.sub.REF
In this circuit, too, there is a problem, associated with the on/off control of the voltage generator unit B1, in that the voltage swing of the output voltage V.sub.BB between the state in which the voltage generator unit B1 is disabled and the state in which the voltage generator unit B1 is activated is excessively large. The circuit of FIG. 2 may be effective in the conventional integrated circuits that use the large substrate bias voltage such as -3.5 volts. In such an integrated circuit, the bias voltage may be allowed to change from -3.5 volts to about -1.5 volts. On the other hand, for the large scale integrated circuits that use the small bias voltage such as -1 volt, this circuit of FIG. 2 is totally inappropriate.
Further, there is a conventional voltage generator circuit as disclosed in the Japanese Laid-open Patent Applications 56-74956, 58-9352 and 60-80266, wherein a variable time constant circuit is provided in a ring oscillator such that the oscillation frequency of the ring oscillator is changed in correspondence to the substrate bias voltage V.sub.BB.
FIG. 3 shows a circuit diagram of the conventional voltage generator circuit that falls in this type. Referring to FIG. 3, the voltage generator circuit includes a ring oscillator 102' in which a time constant circuit including a MOS transistor Q1 and a capacitor C1 and another time constant circuit including a MOS transistor Q2 and a capacitor C2 are connected in series.
In operation, the voltage V.sub.BB is detected by the gate of the MOS transistors Q1 and Q2, and the resistance of the MOS transistors and hence the time constant of the time constant circuit is changed in response to the voltage V.sub.BB When the bias current is small and the magnitude of the bias voltage V.sub.BB is large, the resistance is increased. On the other hand, when there is a large bias current and the magnitude of the bias voltage V.sub.BB is decreased, the resistance of the time constant circuit is decreased and the variation in the biasing voltage level is compensated.
In this conventional circuit, there arises a problem of increased power consumption caused as a result of the blunting of the oscillation waveform that in turn is caused by the time constant circuit. When there appears a blunting in the oscillation waveform, the CMOS inverter forming the ring oscillator is held at an intermediate state between the turned on state and the turned off state. In such an intermediate state, the P-channel MOS transistor and the N-channel MOS transistor connected in series and forming the CMOS inverter, are both turned on and a feed-through current flows through the CMOS inverter. Such a feed-through current flows even in the case where the ring oscillator is oscillating at a low frequency. Thereby, the power consumption of the voltage generator is inevitably increased.